1. Field of the Invention
This invention relates to a random access memory comprising a plurality of memory cells each of which has a flip-flop circuit where a pair of transistors are cross-connected, particularly to a memory cell driver circuit.
2. Description of the Prior Art
A random access memory device, wherein a plurality of memory cells comprising a flip-flop circuit cross-connecting a pair of bipolar transistors as the basic structure are arranged in the form of a matrix is generally known as a high speed RAM (Random Access Memory). In such a memory cell array having the memory cells in the form of a matrix, a level difference exists between the potentials of a selected word line and a non-selected word line. This level difference has so far been selected from the point of view of acquiring a margin at the time of data writing to the memory cells and therefore this value is excessive for data reading. This situation is explained by referring to FIG. 1 to FIG. 3.
FIG. 1 outlines a memory cell array where the memory cells Moo . . . Mno . . . Mom . . . Mnm are arranged in the form of (n+1).times.(m+1) matrix. Each memory cell has, for example in the case of Moo, a flip-flop circuit where the collector and base of a pair of bipolar transistors Qc1, Qc2 are cross-connected. In FIG. 1, Wo . . . Wn are word lines, H0 . . . Hn are hold lines, Bo . . . Bm, Bo . . . Bm are bit lines. The word lines W0 . . . Wn are selected by the word drivers WD0 . . . WDn, while the bit line pairs (B0,B0) . . . (Bm,Bm) are selected by the bit drivers BD0 . . . BDm. The bit drivers BD0 . . . BDm form the current switch circuits in combination with the constant current source I.sub.BS. A current is applied to only a single pair of bit lines as selected by the Y selection signal V.sub.Y0 . . . V.sub.Ym. Only a pair of bit lines is selected. It is also possible to apply a current to all lines. The word drivers WD0 . . . WDn selected by the X selection signals V.sub.X0 . . . V.sub.Xn make only one word line a "H" (High) level and maintain the remaining word lines at a "L" (Low) level. SA is the sense amplifier which forms the detecting system for the contents stored in the memory cell in combination with the transistors (Q.sub.S10,Q.sub.S20) . . . (Q.sub.S1m,Q.sub.S2m) of the the bit line pairs (B.sub.0, B.sub.0) . . . (B.sub.m, B.sub.m). WA is a write amplifier which generates an output V.sub.D .noteq.V.sub.D in accordance with an input Din when the write signal WE is "L", namely during writing, while an output V.sub.D =V.sub.D when the write signal WE is "H", namely during reading.
Explained below with reference to FIG. 2 is the memory array operation with a pair of bit lines B.sub.0, B.sub.0 selected and the word line W.sub.s selected (the selected line is given the subscript s, while the non-selected one is given the subscript N).
FIG. 2 shows a part of FIG. 1, while FIG. 3 shows the potentials of FIG. 2. Namely, when the X selection signal V.sub.xs is "H", the potential V.sub.ws of the word line W.sub.s of selected memory cell M.sub.s0 is kept high by the word driver WD.sub.s. At this time, since the other X selection signal V.sub.XN is a "L", the potential V.sub.WN of the remaining word lines W.sub.N is kept low by means of the word driver WD.sub.N.
The read operation and write operation for the memory cell M.sub.s0 under such condition will be explained by referring to FIG. 3.
The memory cell M.sub.s0 (similar to M.sub.N0) is the emitter detection type cell consisting of two load resistances R.sub.L, Schottky barrier diodes SBD and multi-emitter transistors. The transistors Q.sub.H1 to Q.sub.H4 connected to the hold lines H.sub.s, H.sub.N of the multi-emitter transistors, are the memory holding transistors, while the transistors Q.sub.c1 to Q.sub.c4 connected to the bit lines B.sub.1, B.sub.1, are the driver transistors.
When the transistor Q.sub.H1 of memory cell M.sub.s0 is ON, Q.sub.H2 is OFF, and before selection, the relation V.sub.BS &gt;V.sub.CS is exists between the base voltage V.sub.BS of the transistor Q.sub.c1 and collector voltage V.sub.CS at the time Q.sub.c1 is selected. Here, a voltage difference (V.sub.BS -V.sub.CS) is considered as V.sub.BCS. Namely, the base voltage V.sub.BS is obtained by subtracting a value of voltage drop (this is very small) expressed as the subtraction of the product of the load resistance R.sub.L of Q.sub.c2 and a base current of Q.sub.c1 from the word line voltage V.sub.WS, while the collector voltage V.sub.CS is obtained by subtracting a voltage drop in the forward direction (V.sub.BE) of SBD from V.sub.cc because the the collector current of Q.sub.c1 is sufficiently high and therefore the diode SBD is ON. Thus, as shown in FIG. 3, V.sub.CS is kept low.
The read operation under this condition will be explained below. First, the write amplifier generates output V.sub.D, V.sub.D in accordance with the relation, V.sub.CS &lt;V.sub.D =V.sub.D &lt;V.sub.BS. Since the transistors Q.sub.c1 and Q.sub.s1, Q.sub.c2 and Q.sub.s2 respectively form the current switch, the transistor Q.sub.c1 is ON, while Q.sub.s1 is OFF and the current I.sub.B of bit line B.sub.1 is supplied from the transistor Q.sub.c1. Simultaneously, since V.sub.CS &lt;V.sub.D, the transistor Q.sub.s2 is ON, while Q.sub.c2 is OFF. Thus the current I.sub.B of the bit line B.sub.1 is supplied from the transistor Q.sub.s2. For this reason, the currents viewed from the sense amplifier SA are as follow. I.sub.D =0, I.sub.D =I.sub.B. The information of memory cell M.sub.S0 can be read using the difference between these currents.
Next, the write operation will be explained with the condition of memory cell M.sub.S0 inverted by the write operation. For this purpose, first of all, it is necessary to lower the V.sub.D below collector voltage V.sub.CS by about 200 mV or more, in order to turn Q.sub.c1 to OFF from ON. When V.sub.D is lowered and it becomes equal to V.sub.CS (V.sub.D =V.sub.CS), the current I.sub.B of the bit line B.sub.1 flows equally from both transistors Q.sub.c2 and Q.sub.s2, and moreover when V.sub.D is further lowered (V.sub.D &lt;V.sub.CS), the current I.sub.b flows from the transistor Q.sub.c2 and thereby the transistor Q.sub.c2 is ON, while Q.sub.s2 is OFF. As a result, V.sub.BS is low and the flip-flop is inverted (not indicated in FIG. 3). When V.sub.BS &lt;V.sub.D, even if the V.sub.D remains at a potential equal to that in read operation, the transistor Q.sub.s1 is ON, while transistor Q.sub.c1 is OFF. In such a conventional memory, a level of V.sub.D is boosted generally as indicated in FIG. 3 in order to realize the speed-up of the write operation. Therefore, turning the transistors OFF is performed more quickly.
The problems of the abovementioned write and read operations will be explained. At the time of the write operation, the potential V.sub.WN of the non-selected word line W.sub.N must be such that V.sub.WN &lt;V.sub.D &lt;V.sub.CS. Namely, when the transistor Q.sub.H4 of the non-selected memory cell M.sub.N0 is in the ON state during the write operation, the base voltage V.sub.BN is almost equal to V.sub.WN. When the relation V.sub.WN &gt;V.sub.D is established with V.sub.D lowered for the write operation, the transistor Q.sub.c4 turns ON and the current I.sub.B of the bit line B.sub.1 is supplied from said transistor Q.sub.c4. However, the transistor Q.sub.c2 cannot turns ON sufficiently or it requires excessive long period until it turns ON. In order to avoid such disadvantage, the relation V.sub.CS &gt;V.sub.D &gt;V.sub.WN .apprxeq.V.sub.BN is necessary.
On the other hand, during the read operation, the potential V.sub.WN of the non-selected word line must be lower than V.sub.WS by a constant value, but is not required to be as low as that in the write operation. Namely, it is sufficient if it is a little lower than V.sub.D =V.sub.D. In other words, if V.sub.WN =V.sub.BN =V.sub.D =V.sub.D during the read operation, the current I.sub.B of the bit line B.sub.1 is supplied from both the transistor Q.sub.s2 and Q.sub.c4. Thereby, a difference of currents (I.sub.D -I.sub.D) at the sense amplifier SA is reduced to a half, and thus it becomes difficult to read out the content of the cell M.sub.S0. Such a disadvantage can be avoided by lowering the potential V.sub.WN of the non-selected word line WN than the value V.sub.D =V.sub.D.
However, since the word line potential of the non-selected cell or the word line potential of the selected cell is conventionally constant anytime during the read and write operations, a difference in voltages between the selected word line voltages V.sub.WS and non-selected word line voltage V.sub.WN during read operation has been excessively high. This means that the selected word line voltage rises drastically during the change over to selection from the non-selection condition, namely in the transient condition to the read operation. Since it is necessary to charge the stray capacitance of the word lines to raise the word line voltage, a longer period is required for raising the word line voltage. Moreover, such problem has brought about the disadvantage that the read operation speed is lowered.
Such disadvantage can be eliminated by changing the voltage level difference between the selected word line and non-selected word line for the read and write operations. Moreover, the same effect can be obtained by changing the single selected word line level for the read and write operations.
This example of changing the selected word line level will be explained by referring to the schematic diagram of FIG. 4. The circuit shown in FIG. 4 illustrates the decoders DEC.sub.0 to DEC.sub.n and word drivers WD.sub.0 to WD.sub.n. In regard to the decoders DEC.sub.0 to DEC.sub.n, only a part is shown. In the decoders DEC.sub.0 to DEC.sub.n, the transistors (T.sub.10, T.sub.20, T.sub.30) to (T.sub.1n, T.sub.2n, T.sub.3n) respectively form the current switches for I.sub.xw, while the transistors (T.sub.40, T.sub.50) to (T.sub.4n, T.sub.5n) respectively form the current for I.sub.x. Only one of the decoder signals S.sub.0 to S.sub.n is a low (L) level and the transistors (T.sub.10, T.sub.50) are OFF, if S.sub.0 is the L level. Thus, one of the selection signal voltages V.sub.X0 to V.sub.Xn becomes a high, H, level. Thereby, one of the word lines WL.sub.0 to WL.sub.n becomes H level and is selected. At this time, all of the remaining signals among S.sub.0 to S.sub.n are at a H level, turning ON the relevant transistors (T.sub.10, T.sub.50) and resultingly all of the remaining selection signal voltages V.sub.X0 to V.sub.Xn are a L level. Thus, the relevant word line is a L level.
The level of a word line WL.sub.0 to WL.sub.n when selected is higher than that at the time of non-selection. But the select level at the time of the write operation is higher than that at the time of the read operation as shown in FIG. 5. In other words, the write control signal WE is a H during the read operation or a L during the write operation. During the read operation, at the current switches T.sub.10, T.sub.20, T.sub.30 (FIG. 4) which select the word line, for example, WL.sub.0, the transistor T.sub.20 is ON. At the current switch comprising the transistors T.sub.40, T.sub.50, the transistor T.sub.40 is ON and a current of the current source I.sub.x flows through the transistor T.sub.40. On the other hand, when the transistor T.sub.20 is ON, the current I.sub.XW flows through the load resistance R.sub.X. Therefore, the selection signal voltage V.sub.X0 is lowered to (V.sub.CC -R.sub.X I.sub.XW) as indicated in FIG. 5. This voltage is higher than the level {V.sub.CC -R.sub.X (I.sub.X +I.sub.XW)} of the non-selection condition, but is lower than the level V.sub.CC in the selecting condition.
Meanwhile, since S.sub.0 =L, WE=L during the write operation, the transistors T.sub.30, T.sub.40 are ON, while T.sub.10, T.sub.20, T.sub.50 are OFF. Therefore, the currents I.sub.x, I.sub.XW do not flow into the resistor R.sub.X. Thereby, the selection signal voltage V.sub.X0 becomes the highest power supply voltage V.sub.CC. At the time of non selection, S.sub.0 is a H level (similar to the other non-selection word), the transistors T.sub.10, T.sub.50 are ON and the currents I.sub.X, I.sub.XW flow through the resistance R.sub.X. As a result, the selection signal voltage V.sub.X0 is the lowest level shown in FIG. 5.
By the aforementioned operation, the potential of the word line during of the write operation can be made larger than that during the read operation. However, the circuit shown in FIG. 4 requires the current sources I.sub.X, I.sub.XW for each of the decoders DEC.sub.0 to DEC.sub.n which are provided to the word drivers WD.sub.0 to WD.sub.n. Therefore there is a disadvantage in that power consumption is large. Furthermore, the multi-emitter type transistors are used and many elements are also used in each of the decoders DEC.sub.0 to DEC.sub.n, so that, the structure is complicated.